WAYTOGOFAST main objective is to establish a Pilot Line in ST-Crolles and SOITEC Bernin to promote and sustain the FD-SOI technologies in Europe for the next years.

This pilot line will offer an optimized Power-Performance-Area-Cost (PPAC) trade-off for FD-SOI technology platform based on Fully Depleted (FD) devices built on advanced Silicon On Insulator (SOI) substrate. 

28nm FD-SOI Roadmap

For this purpose, the project will work on the most suitable generations of FD-SOI technologies to answer the market requirements in the next 4 years.

At the end of the project the pilot line should be ready to ramp in production with a qualified technology having its reliability demonstrated. During the project timeframe the SOI substrate for this FDSOI technology will pass industrial maturity readiness stage (SOITEC PILOT LINE), and so will the FD CMOS technology platform built on it by STMicroelectronics (ST) and Global Foundries (GF).

Innovation on substrate supports FD-SOI roadmap